The present invention relates to high-speed communications applications, and more particularly relates to a differential T-coil impedance-matching circuit included in an integrated circuit (IC) system to match an impedance between the IC system's off-chip package (e.g., differential high-speed communications channel or circuit) and the on-chip circuitry required to interface and exchange data with the channel or off-chip package in a much reduced area within the IC comprising the IC system.
High-speed I/O circuits require an effective impedance match between an off-chip package and the on-chip circuitry to ensure efficient power transfer and signal integrity, particularly during differential high-speed I/O circuit applications. The off-chip package, referred to interchangeably herein as channel, high-speed channel, differential high-speed channel, circuit and like expressions, typically behaves as a transmission line with a real characteristic impedance (Z0). In order to achieve a good impedance match between the off-chip package and the on-chip I/O circuit, the on-chip I/O circuit should present a real impedance that equals as close as possible to the package transmission line impedance (Z0). Capacitive loading on-chip, however, tends to degrade the impedance match between the off-chip package and on-chip I/O circuit. The capacitive loading may derive from the on-chip I/O circuit and from electrostatic discharge (ESD) protection circuits, which are typically attached to the I/O pin to protect the I/O circuitry from ESD events. Conventional efforts and attempts to match such impedances include placing a termination resistor on-chip and attached to the I/O pin.
FIG. 1a herein depicts a conventional IC system 10 including an off-chip package or channel 15 and an on-chip I/O circuit 20 arranged for high-speed differential communications operation. The channel and on-chip I/O circuit are separated by a package/chip interface indicated by the dashed line 25. I/O circuit 20 includes two terminations, Rterm 1, Rterm 2, and two capacitive elements representing the capacitance of the on-chip circuitry including the capacitance of the ESD protection devices, Cload 1 and Cload 2. Rterm 1 and Cload 1 comprise a differential circuit receive/transmit circuit RX/TX 1, where Rterm 2 and Cload 2 comprise differential receive/transmit circuit RX/TX 2. Termination resistors Rterm 1, Rterm 2, are included in the on-chip circuit to match impedance of the on-chip circuit to the impedance of the off-chip package 15 (as mentioned above). While the frequency of operation (I/O data rate) is sufficiently low, the inherent I/O and ESD capacitances in parallel electrically with the termination resistors will have a relatively negligible effect on the impedance seen or present at the chip's I/O pin (as “seen” by the I/O channel). But as such frequency of operation increases, the I/O circuit and ESD capacitances degrade the impedance match between the channel and on-chip I/O circuitry. In such case, IC designers are compelled to implement I/O circuit design changes to ensure signal integrity, particularly for very high-speed I/O operations.
One known attempt at a solution to such impedance mismatch with increasing frequency of operation is to add an inductance to the on-chip circuit. FIG. 1b depicts a conventional I/O circuit 50 including 1:1 transformers in the form of conventional T-coils (T-coil 1, T-coil 2). Each of the T-coils includes a link to the off-chip package (channel) connected to firsts ends of a primary inductance Lp and capacitance Cfb, where the other ends of same are connected through a second or secondary inductance Ls. The Lp side of inductance Ls is shown connected through a load capacitance to ground, and the Cfb side of inductance Ls is connected through Rterm1 to ground. The skilled artisan should note that FIG. 1b is a circuit model representation. The second T-coil (circuit model) is the equivalent to the first T-coil circuit (model). The coupling factors or coefficients between the primary and secondary inductances in each T-coil (between Ls and Lp), are identified by constant K.
The added inductance (one T-coil comprising Lp and Ls for each side of the differential high-speed I/O circuit) has the effect of compensating out the capacitance with the increasing frequency of operation, essentially matching the impedance of the high-speed I/O circuit with that of the channel or package impedance. Various circuit layouts may be implemented to achieve such compensation (and impedance matching), including the T-coils 52, 54 (1:1 transformers) disposed between the I/O pin of the off-chip package or differential high-speed I/O channel and the I/O circuit including ESD protection.
Where conventional T-coils are used in conventional high-speed differential IC designs to improve the impedance match, the T-coils must be placed between the I/O pin (for example, at a C4 or wire bound pad) and the on-chip circuit. Doing so within an integrated circuit, however, requires fabricating the T-coils from available on-chip interconnect metallization(s). One particular T-coil design constraint is its dependency upon the size of the capacitance, or capacitive reactance that requires compensation. A larger capacitance requires a larger T-coil inductance for effective compensation. For modern communications channels, T-coil inductances on an order of 1 nH (composite inductance) are required to compensate the I/O circuit and ESD capacitances. T-coils of this size may require on-chip areas as large as 100 μm×100 μm to be cleared of all other circuitry and wiring channels.
This tradeoff of chip area available for functional circuitry and T-coil chip area can drive up the cost of the chip as a whole. In applications where the high-speed I/O channels are constructed for differential I/O operation, two T-coils (one T-coil for each half) are required per I/O circuit (per I/O channel interface), driving up the IC area required to accommodate the T-coils, therefore reducing area that could be available for other functional on-chip circuitry.
What would be desirable therefore in the art of integrated circuit (IC) design, including ICs and IC system designed for high-speed differential communications operations and applications is a differential T-coil impedance matching circuit that substantially matches the impedance between an IC's on-chip I/O circuitry and the off-chip package and channel, but which requires much less, and preferably one half (½) of the on-chip area typically required for fabrication to implement the T-coils, and their associated functional circuitry in an IC system.